A phenomenon of current leakage occurs in CMOS inverter circuits when driven with an NMOS transfer gate. The phenomenon is related to the fact that the P channel transistor portion of the CMOS inverter does not receive an adequate amount of gate voltage for completely cutting off the channel when the logic level to the input of the transfer gate is in the 1 state. This small amount of leakage current is multiplied many times within an integrated circuit chip by the usage of a multiplicity of CMOS inverters.
One patent of particular interest in U.S. Pat. No. 4,593,212 entitled, "TTL to CMOS Input Buffer" by Ysvager, wherein there is disclosed a buffer circuit utilizing a CMOS inverter wherein the P channel transistor is provided with a relatively low gain so that there is very little current flow through the inverter when the input signal to the buffer is at a low voltage logic high. Aside from the selection of the low gain for one of the CMOS transistors a switch is coupled between the power supply and the output of the buffer such that the switch couples the full power supply voltage to the output of the CMOS inverter when the input signal is switching from a logic high to a logic low.
Another patent of interest for it's showing of the prevention of excessive current flow through a CMOS inverter during its switching from one logic state to another is U.S. Pat. No. 4,518,873 entitled, "Buffer Circuit for Driving a C-MOS Inverter", by Ysuzuki et al. In the preferred embodiment of this patent, a CMOS inverter is driven by a buffer circuit. A first and a second inverter with each of the inverters including at least three transistors are connected in series to form the buffer circuit. One of the three transistors in each inverter is driven by a delay circuit so that during a transition period of the CMOS inverter, simultaneous conduction of current through the CMOS inverter is prevented.
Another patent of interest is U.S. Pat. No. 4,567,385 entitled, "Power Switched Logic Gates", by S. L. Falater et al. The circuit embodiments of this patent solve the problem of current leakage by switchably connecting the low power terminal to the gates and inverter logic circuits to the high power terminal so that no voltage differential appears across the circuits in one logic state. The lack of a voltage differential in turn eliminates the flow of leakage current.